No prior art is known wherein FET construction may proceed to the point where doping is provided for selected FETs to complete their manufacture and provide a 1 state of logic whereas the other cells are undoped to preclude the fabrication of complete FETs which signify the other state of logic.
The closest prior art known is U.S. Pat. No. 4,231,051 issued to the same inventors on Oct. 28, 1980, which discloses a basic process subject to modification to produce the products of the present invention. Such process, however, does not produce a high density ROM comprised of FETs and non-FETs for programming. Nor does the subject process require any second layer of polysilicon to produce the FETs and non-FETs. Nor does the referenced process employ a programming mask. Nor does the prior art show any inventoriable ROMs which are processed to the point of determining which cells will comprise FETs and which will not and then the ROM is completed according to the customer's specifications immediately.